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To browse Academia. Skip to main content. By using our site, you agree to our collection of information through the use of cookies. To learn more, view our Privacy Policy. Log In Sign Up. Venkat Challagulla. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conven- tional nonvolatile memory programmer.

By combining a versatile 8-bit CPU with Flash AT89C51 on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. In this application, it uses strong internal pullups software selectable power saving modes. The Idle Mode when emitting 1s. The contents of the P2 Special Function Register.

Power-down Mode saves the RAM contents but freezes Port 2 also receives the high-order address bits and some the oscillator disabling all other chip functions until the next control signals during Flash programming and verification. When 1s P3. Port 0 may also be configured to be the multiplexed low- P3. In this mode P0 has internal P3. Port 0 also receives the code bytes during Flash program- P3. External pullups are required during program P3. Port 1 Port 3 also receives some control signals for Flash pro- gramming and verification.

RST When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Reset input. A high on this pin for two machine cycles while Port 1 pins that are externally being pulled low will source the oscillator is running resets the device. Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory.

As inputs, ing or clocking purposes. There are no requirements on the duty cycle of the external If desired, ALE operation can be disabled by setting bit 0 of clock signal, since the input to the internal clocking circuitry SFR location 8EH.

Otherwise, the pin is mum voltage high and low time specifications must be weakly pulled high. Setting the ALE-disable bit has no observed. The mode is invoked by gram memory. The content of the on-chip RAM and all the spe- When the AT89C51 is executing code from external pro- cial functions registers remain unchanged during this gram memory, PSEN is activated twice each machine mode.

The idle mode can be terminated by any enabled cycle, except that two PSEN activations are skipped during interrupt or by a hardware reset. EA must be strapped to GND in the internal reset algorithm takes control. On-chip hardware order to enable the device to fetch code from external pro- inhibits access to internal RAM in this event, but access to gram memory locations starting at H up to FFFFH.

To eliminate the possibility of Note, however, that if lock bit 1 is programmed, EA will be an unexpected write to a port pin when Idle is terminated by internally latched on reset. This pin also receives the volt programming enable volt- Figure 1. External Clock Drive Configuration ters retain their values until the power-down mode is terminated.

The only exit from power-down is a hardware reset. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unpro- grammed U or can be programmed P to obtain the additional features listed in the table below.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec- Power-down Mode essary that the latched value of EA be in agreement with In the power-down mode, the oscillator is stopped, and the the current logic level at that pin in order for the device to instruction that invokes power-down is the last instruction function properly.

During a write cycle, an and ready to be programmed. The programming interface attempted read of the last byte written will result in the com- accepts either a high-voltage volt or a low-voltage plement of the written datum on PO. Once the write cycle V CC program enable signal. The low-voltage program- has been completed, true data are valid on all outputs, and ming mode provides a convenient way to program the the next cycle may begin.

The respective BUSY. The lock bits xxxx xxxx-5 cannot be verified directly. Verification of the lock bits is yyww yyww achieved by observing that their features are enabled. The chip erase operation must be executed before the code memory can be re-programmed. The AT89C51 code memory array is programmed byte-by- Reading the Signature Bytes: The signature bytes are byte in either programming mode. To program any non- read by the same procedure as a normal verification of blank byte in the on-chip Flash Memory, the entire memory locations H, H, and H, except that P3.

The values returned are Programming Algorithm: Before programming the as follows. Input the desired memory location on the address lines. Input the appropriate data byte on the data lines. Programming Interface 3. Activate the correct combination of control signals.

Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combi- 4. The write operation cycle is self- ming mode.

Flash array or the lock bits. The byte-write cycle is All major programming vendors offer worldwide support for self-timed and typically takes no more than 1. Please contact your local Repeat steps 1 through 5, changing the address programming vendor for the appropriate software revision. Figure 3.

Programming the Flash Figure 4. P1 ADDR. Only used in volt programming mode. This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin other conditions beyond those indicated in the with Respect to Ground Exposure to absolute maximum rating Maximum Operating Voltage DC Output Current Pins are not guaranteed to sink current greater than the listed test conditions.

For timing purposes, a port pin is no longer floating logic 1 and 0. Timing measurements when a mV change from load voltage occurs. A are made at VIH min. Cheyenne Mtn. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein.

No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Printed on recycled paper. Terms and product names in this document may be trademarks of others.

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89C51 Datasheet

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AT89C51 Datasheet PDF

Note: The AT89C51 datasheet of the Microcontroller and more detailed Features can be found at the bottom of this page. The AT89C51 is an age old 8-bit microcontroller from the Atmel family. It works with the popular architecture and hence is used by most beginners till date. It is a 40 pin IC package with 4Kb flash memory.

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